The specification for the PCIe Gen3 (Peripheral Component Interconnect Express, third generation starting with version 3.0) protocol introduces 128-to-130 bit encoding. A serial stream has TLPs (Transaction Layer Packets), DLLPs (Data Link Layer Packets) and SKIP OS' (Ordered Sets) with a 2-bit sync-header followed by a 128 bit data pattern. The sync header can be either 01 or 10. The sync-header indicates to a PCIe receiver whether the following 128-bits are a data block or an ordered set. Before the receiver's link layer processes incoming TLPs, the sync headers are stripped out.
The upstream PHY layer has a serial to parallel converter which converts the incoming 1b@8GT/s data stream into an 8b@1GT/s parallel path for easier management. However, stripping out these 2 bit sync headers every 16 cycles of the 1 GHz clock, creates an upstream dead cycle (a cycle with no data) after every 64 cycles of the 1 GHz clock of data. The dead cycles can occur in the middle of a TLP when the link layer is processing incoming data. This can disrupt the processing of the TLP and lead to errors in the results.